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october 2007 rev. 3 1/26 26 ST1S10 3 a, 900 khz, mono lithic synchronous step-down regulator features step-down current mode pwm regulator output voltage adjustable from 0.8 v input voltage from 2.5 v up to 18 v 2% dc output voltage tolerance synchronous rectification inhibit function synchronizable switching frequency from 400 khz up to 1.2 mhz internal soft start dynamic short circuit protection typical efficiency: 90% 3 a output current capability stand-by supply current: max 6 a over temperature range operative junction temp: from -25c to 125c applications consumer ? stb, dvd, dvd recorders, tv, vcr, car audio, lcd monitors networking ? xdsl, modems, dc-dc modules computer ? optical storage, hd drivers, printers, audio/graphic cards industrial and security ? battery chargers, dc-dc converters, pld, pla, fpga, led drivers description the ST1S10 is a high efficiency step-down pwm current mode switching regulator capable of providing up to 3 a of output current. the device operates with an input supply range from 2.5 v to 18 v and provides an adjustable output voltage from 0.8 v (v fb ) to 0.85*v in_sw [v out = v fb *(1+r1/r2)]. it operates either at a 900 khz fixed frequency or can be synchronized to an external clock (from 400 khz to 1.2 mhz). the high switching frequency allows the use of tiny smd external components, while the integrated synchronous rectifier eliminates the need for a schottky diode. the ST1S10 provides excellent transient response, and is fully protected against thermal overheating, switching over-current and output short circuit. the ST1S10 is the ideal choice for point-of-load regulators or ldo pre-regulation. powerso-8 dfn8 (4x4mm) table 1. device summary part number package dfn8 (4x4 mm) powerso-8 ST1S10 ST1S10pur ST1S10phr www.st.com
contents ST1S10 2/26 contents 1 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 external components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2.1 input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.3 output capacitor (v out > 2.5 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.4 output capacitor (0.8 v < v out < 2.5 v) . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.5 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.6 inductor (v out > 2.5 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.7 inductor (0.8 v < v out < 2.5 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.8 function operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.8.1 sync operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.8.2 inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.8.3 ocp (over-current protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.8.4 scp (short circuit protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.8.5 scp and ocp operation with high capacitive load . . . . . . . . . . . . . . . . 12 6 layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7 diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8 typical performance characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
ST1S10 application circuit 3/26 1 application circuit figure 1. typical application circuit ST1S10 12v l1 3.3h c1 4.7f sw fb c2 22f vin_sw sync en 5v ? 3a r1 r2 vin_a agnd pgnd c3 0.1f ST1S10 12v l1 3.3h c1 4.7f sw fb c2 22f vin_sw sync en 5v ? 3a 5v ? 3a r1 r2 vin_a agnd pgnd c3 0.1f
pin configuration ST1S10 4/26 2 pin configuration figure 2. pin connections (top view fo r powerso-8, bottom view for dfn8) powerso-8 dfn8 (4x4) table 2. pin description pin n symbol name and function 1v in_a analog input supply voltage to be tied to v in supply source 2 inh (en) inhibit pin active low. connect to v in_a if not used 3v fb feedback voltage for connection to external voltage divider to set the v out from 0.8v up to 0.85*v in_sw . (see output voltage selection paragraph 5.5 ) 4 agnd analog ground 5 sync synchronization and frequency select. connect sync to gnd for 900 khz operation, or to an external clock from 400 khz to 1.2 mhz. (see sync operation paragraph 5.8.1 ) 6v in_sw power input supply voltage to be tied to v in power supply source 7 sw switching node to be connected to the inductor 8 pgnd power ground epad epad exposed pad to be connected to ground
ST1S10 maximum ratings 5/26 3 maximum ratings note: absolute maximum ratings are the values beyond which damage to the device may occur. functional operation under these conditions is not implied. table 3. absolute maximum ratings symbol parameter value unit v in_sw positive power supply voltage -0.3 to 20 v v in_a positive supply voltage -0.3 to 20 v v inh inhibit voltage -0.3 to v in_a v v sw output switch voltage -0.3 to 20 v v fb feedback voltage -0.3 to 2.5 v i fb fb current -1 to +1 ma sync synchronization -0.3 to 6 v t stg storage temperature range -40 to 150 c t op operating junction temperature range -25 to 125 c table 4. thermal data symbol parameter powerso-8 dfn8 unit r thja thermal resistance junction-ambient 40 40 c/w r thjc thermal resistance junction-case 12 4 c/w
electrical characteristics ST1S10 6/26 4 electrical characteristics table 5. electrical characteristics v in = v in_sw = v in_a = v inh = 12 v, v sync = gnd, v out = 5 v, i out = 10 ma, c in = 4.7 f +0.1 f, c out = 22 f, l1 = 3.3 h, t j = -25 to 125c (unless otherwise specified, refer to the typical application circuit. typical values assume t j = 25c) symbol parameter test cond itions min. typ. max. unit v fb feedback voltage t j = 25c 784 800 816 mv t j = -25c to 125c 776 800 824 mv i fb v fb pin bias current 600 na i q quiescent current v inh > 1.2 v, not switching 1.5 2.5 ma v inh < 0.4 v 2 6 a i out output current (1) v in = 2.5 v to 18 v v out = 0.8 v to 13.6 v (2) 3.0 a v inh inhibit threshold device on 1.2 v device off 0.4 v i inh inhibit pin current 2 a %v out / v in reference line regulation 2.5 v < v in < 18 v 0.4 %v out / v in %v out / i out reference load regulation 10 ma < i out < 3 a 0.5 %v out / i out pwm fs pwm switching frequency v fb = 0.7 v, sync = gnd t j = 25c 0.7 0.9 1.1 mhz d max maximum duty cycle (2) 85 90 % r dson -n nmos switch on resistance i sw = 750 ma 0.10 r dson -p pmos switch on resistance i sw = 750 ma 0.12 i swl switch current limitation 5.0 a efficiency i out = 100 ma to 300 ma 85 % i out = 300 ma to 3 a 90 % t shdn thermal shut down 150 c t hys thermal shut down hysteresis 15 c v out / i out output transient response 100 ma < i out < 1 a, t r = t f 500 ns 5%v o v out / i out @i o =short short circuit removal response (overshot) 10 ma < i out < short 10 %v o f sync sync frequency capture range v in = 2.5 v to 18 v, v sync = 0 to 5 v 0.4 1.2 mhz sync wd sync pulse width v in = 2.5 v to 18 v 250 ns v il_sync sync input threshold low v in = 2.5 v to 18 v 0.4 v v ih_sync sync input threshold high v in = 2.5 v to 18 v 1.6 v
ST1S10 electrical characteristics 7/26 symbol parameter test cond itions min. typ. max. unit i il, i ih sync input current v in = 2.5 v to 18 v, v sync = 0 or 5 v -10 +10 a uvlo under voltage lock-out threshold v in rising 2.3 v hysteresis 200 mv 1. guaranteed by design, but not tested in production. 2. see output voltage selection paragraph 5.5 for maximum duty cycle conditions. table 5. electrical characteristics (continued) v in = v in_sw = v in_a = v inh = 12 v, v sync = gnd, v out = 5 v, i out = 10 ma, c in = 4.7 f +0.1 f, c out = 22 f, l1 = 3.3 h, t j = -25 to 125c (unless otherwise specified, refer to the typical application circuit. typical values assume t j = 25c)
application information ST1S10 8/26 5 application information 5.1 description the ST1S10 is a high efficiency synchronous step-down dc-dc converter with inhibit function. it provides up to 3 a over an input voltage range of 2.5 v to 18 v, and the output voltage can be adjusted from 0.8 v up to 85% of the input voltage level. the synchronous rectification removes the need for an external schottky diode and allows higher efficiency even at very low output voltages. a high internal switching frequency (0.9 mhz) allows the use of tiny surface-mount components, as well as a resistor divider to set the output voltage value. in typical application conditions, only an inductor and 3 capacitors are required for proper operation. the device can operate in pwm mode with a fixed frequency or synchronized to an external frequency through the sync pin. the current mode pwm architecture and stable operation with low esr smd ceramic capacitors results in low, predictable output ripple. no external compensation is needed. to maximize power conversion efficiency, the ST1S10 works in pulse skipping mode at light load conditions and automatically switches to pwm mode when the output current increases. the ST1S10 is equipped with thermal shut down protection activated at 150c (typ.). cycle-by-cycle short circuit protection provi des protection against shorted outputs for the application and the regulator. an internal soft start for start-up current limiting and power on delay of 275 s (typ.) helps to reduce inrush current during start-up. 5.2 external components selection 5.2.1 input capacitor the ST1S10 features two v in pins: v in_sw for the power supply input voltage where the switching peak current is drawn, and v in_a to supply the ST1S10 internal circuitry and drivers. the v in_sw input capacitor reduces the current peaks drawn from the input power supply and reduces switching noise in the ic. a high power supply source impedance requires larger input capacitance. for the v in_sw input capacitor the rms current rating is a critical parameter that must be higher than the rms input current. the maximum rms input current can be calculated using the following equation: where is the expected system efficiency, d is the duty cycle and i o is the output dc current. the duty cycle can be derived using the equation: d = (v out + v f ) / (v in -v sw ) where v f is the voltage drop across the internal nmos, and v sw represents the voltage drop across the internal pdmo s. the minimum duty cycle (at v in_max ) and the maximum d d 2 - d i i 2 2 o rms + ? ? = d d 2 - d i i 2 2 o rms + ? ? =
ST1S10 application information 9/26 duty cycle (at v in_min ) should be considered in order to determine the max i rms flowing through the input capacitor. a minimum value of 4.7 f for the v in_sw and a 0.1 f ceramic capacitor for the v in_a are suitable in most application conditions. a 10 f or higher ceramic capacitor for the v in_sw and a 1 f or higher for the v in_a are recommended in cases of higher power supply source impedance or where long wires are needed between the power supply source and the v in pins. the above higher input capacitor values are also recommended in cases where an output capacitive load is present (47 f < c load < 100 f), which could impact the switching peak current drawn from the input capacitor during the start-up transient. in cases of very high output capacitive loads (c load > 100 f), all input/output capacitor values shall be modified as described in the ocp and scp operation section 5.8.5 of this document. the input ceramic capacitors should have a voltage rating in the range of 1.5 times the maximum input voltage and be located as close as possible to v in pins. 5.3 output capacitor (v out > 2.5 v) the most important parameters for the output capacitor are the capacitance, the esr and the voltage rating. the capacitance and the esr affect the control loop stability, the output ripple voltage and transient response of the regulator. the ripple due to the capacitance can be calculated with the following formula: v ripple(c) = (0.125 x i sw ) / (f s x c out ) where f s is the pwm switching frequency and i sw is the inductor peak-to-peak switching current, which can be calculated as: i sw = [(v in - v out ) / (f s x l)] x d where d is the duty cycle. the ripple due to the esr is given by: v ripple (esr) = i sw x esr the equations above can be used to define the capacitor selection range, but final values should be verified by testing an evaluation circuit. lower esr ceramic capacitors are usually recommended to reduce the output ripple voltage. capacitors with higher voltage rating s have lower esr values, resulting in lower output ripple voltage. also, the capacitor esl value impacts the output ripple voltage, but ceramic capacitors usually have very low esl, making ripple volt ages due to the esl negligible. in order to reduce ripple voltages due to the parasitic inductive effect, the output capacitor connection paths should be kept as short as possible. the ST1S10 has been designed to perform best with ceramic capacitors. under typical application conditions a minimum ceramic capacitor value of 22 f is recommended on the output, but higher values are suitable considering that the control loop has been designed to work properly with a natural output lc frequency provided by a 3.3 h inductor and 22 f output capacitor. if the high capacitive load application circuit shown in figure 3 is used, a 47 f (or 2 x 22 f capacitors in parallel) could be needed as described in the ocp and scp operation section 5.8.5 . of this document.
application information ST1S10 10/26 the use of ceramic capacitors with voltage ratings in the range of 1.5 times the maximum output voltage is recommended. 5.4 output capacitor (0.8 v < v out < 2.5 v) for applications with lower output voltage levels (v out < 2.5 v) the output capacitance and inductor values should be selected in a way th at improves the dc-dc co ntrol loop behavior. in this output condition two cases must be considered: v in > 8 v and v in < 8 v. for v in < 8 v the use of 2 x 22 f capacitors in parallel to the output is recommended, as shown in figure 4. for v in > 8 v, a 100 f electrolytic capacitor with esr < 0.1 should be added in parallel to the 2 x 22 f output capacitors as shown in figure 5. 5.5 output voltage selection the output voltage can be adjusted from 0.8 v up to 85% of the input voltage level by connecting a resistor divider (see r1 and r2 in the typical application circuit) between the output and the v fb pin. a resistor divider with r2 in the range of 20 k is a suitable compromise in terms of current consumption. once the r2 value is selected, r1 can be calculated using the following equation: r1 = r2 x (v out - v fb ) / v fb where v fb = 0.8 v (typ.). lower values are suitable as well, but will incr ease current consumptio n. be aware that duty cycle must be kept below 85% at a ll application conditions, so that: d = (v out + v f ) / (v in -v sw ) < 0.85 where v f is the voltage drop across the internal nmos, and v sw represents the voltage drop across the internal pdmos. note that once the output current is fixed, higher v out levels increase the power dissipation of the device leading to an increase in the operating junction temperature. it is recommended to select a v out level which maintains the junc tion temperature below the thermal shut-down protection threshold (150c typ.) at the rated output current. the following equation can be used to calculate the junction temperature (t j ): t j = {[v out x i out x r thja x (1- )] / } +t amb where r thja is the junction-to-ambient thermal resistance, is the efficiency at the rated i out current and t amb is the ambient temperature. to ensure safe operating conditions the application should be designed to keep t j < 140c. 5.6 inductor (v out > 2.5 v) the inductor value fixes the ripple current flowing through output capacitor and switching peak current. the ripple current should be kept in the range of 20-40% of i out_max (for example it is 0.6 - 1.2 a at i out = 3 a). the approximate inductor value can be obtained with the following formula: l = [(v in - v out ) / i sw ] x t on
ST1S10 application information 11/26 where t on is the on time of the internal switch, given by: t on = d/f s the inductor should be selected with sa turation current (i sat ) equal to or higher than the inductor peak current, which can be calculated with the following equation: i pk = i o + ( i sw /2), i sat i pk the inductor peak current must be designed so that it does not exceed the switching current limit. 5.7 inductor (0.8 v < v out < 2.5 v) for applications with lower output voltage levels (v out < 2.5 v) the description in the previous section is still valid but it is recommended to ke ep the inductor values in a range from 1h to 2.2 h in order to improve the dc-dc control loop behavior, and increase the output capacitance depending on the v in level as shown in the figure 4 and figure 5. in most application conditions a 2.2 h inductor is the best compromise between dc-dc control loop behavior and output voltage ripple. 5.8 function operation 5.8.1 sync operation the ST1S10 operates at a fixed frequency or can be synchronized to an external frequency with the sync pin. the ST1S10 switches at a frequency of 900 khz when the sync pin is connected to ground, and can synchronize the switching frequency between 400 khz to 1.2 mhz from an external clock applied to the sync pin. when the sync feature is not used, this pin must be connected to ground with a path as short as possible to avoid any possible noise injected in the sync internal circuitry. 5.8.2 inhibit function the inhibit pin can be used to turn off the regulator when pulled down, thus drastically reducing the current consumption down to less than 6 a. when the inhibit feature is not used, this pin must be tied to v in to keep the regulator output on at all times. to ensure proper operation, the signal source used to drive the inhibit pin must be able to swing above and below the specified thresholds listed in the electrical characteristics section under v inh . any slew rate can be used to drive the inhibit pin. 5.8.3 ocp (over-current protection) the ST1S10 dc-dc converter is equipped with a switch over-current protection. in order to provide protection for the application and the internal power switches and bonding wires, the device goes into a shutdown state if the switch current limit is reached and is kept in this condition for the t off period (t off(ocp) = 135 s typ.) and turns on again for the t on period (t on(ocp) = 22 s typ.) under typical application conditions. this operation is repeated cycle by cycle. normal operation is resumed when no over-current is detected.
application information ST1S10 12/26 5.8.4 scp (short ci rcuit protection) in order to protect the entire application and reduce the total power dissipation during an overload or an output short circuit condition, the device is equipped with dynamic short circuit protection which works by internally monitoring the v fb (feedback voltage). in the event of an overload or output short circuit, if the v out voltage is reduced causing the feedback voltage (v fb ) to drop below 0.3 v (typ.), the device goes into shutdown for the t off time (t off(scp) = 288 s typ.) and turns on again for the t on period (t on(scp) = 130 s typ.). this operation is repeated cycle by cycle, and normal operation is resumed when no overload is detected (v fb > 0.3 v typ.) for the full t on period. this dynamic operation can greatly reduce the power dissipation in overload conditions, while still ensuring excellent power- on startup in most conditions. 5.8.5 scp and ocp operation with high capacitive load thanks to the ocp and scp circuit, ST1S10 is strongly protected against damage from short circuit and overload. however, a highly capacitive load on the output may cause difficulties during start-up. this can be resolved by using the modified application circuit shown in figure 3 , in which a minimum of 10 f for c1 and a 4.7 f ceramic capacitor for c3 are used. moreover, for c load > 100 f, it is necessary to add the c4 capacitor in parallel to the upper voltage divider resistor (r1) as shown in figure 3. the recommended value for c4 is 4.7 nf. note that c4 may impact the control loop response and should be added only when a capacitive load higher than 100 f is continuously present. if the high capacitive load is variable or not present at all times, in addition to c4 an increase in the output ceramic capacitor c2 from 22 f to 47 f (or 2 x 22 f capacitors in parallel) is recommended. also in this case it is suggested to further increase the input capacitors to a minimum of 10 f for c1 and a 4.7 f ceramic capacitor for c3 as shown in figure 3. (*) see ocp and scp descriptions for c2 and c4 selection figure 3. application schematic for heavy capacitive load ST1S10 12v l1 3.3h c1 10f sw fb vin_sw sync en r1 r2 vin_a agnd pgnd c3 4.7f c2(*) 22f 5v ? 3a c4 (*) 4.7nf c load load output load ST1S10 12v l1 3.3h c1 10f sw fb vin_sw sync en r1 r2 vin_a agnd pgnd c3 4.7f c2(*) 22f 5v ? 3a 5v ? 3a c4 (*) 4.7nf c load c load load output load
ST1S10 application information 13/26 figure 4. application schematic for low output voltage (v out < 2.5 v) and 2.5 v < v in < 8 v ST1S10 v in<8v l1 2.2h c1 10f sw fb vin_sw sync en r1 r2 vin_a agnd pgnd c3 0.1f c2 2x22f 0.8vST1S10 v in<8v l1 2.2h c1 10f sw fb vin_sw sync en r1 r2 vin_a agnd pgnd c3 0.1f c2 2x22f 0.8vST1S10 8vST1S10 8v layout considerations ST1S10 14/26 6 layout considerations layout is an important step in design for all switching power supplies. high-speed operation (900 khz) of the ST1S10 device demands careful attention to pcb layout. care must be taken in board layout to get device performance, otherwise the regulator could show p oor line and load regulat ion, stability issues as well as emi problems. it is critical to provide a low inductance, impedance ground path. therefore, use wide and short traces for the main current paths. the input capacitor must be placed as close as possible to the ic pins as well as the inductor and output capacitor. use a common ground node for power ground and a different one for control ground (agnd) to minimize the effects of ground noise. connect these ground nodes together underneath the device and make sure that small signal components returning to the agnd pin and do not share the high current path of c in and c out . the feedback voltage sense line (v fb ) should be connected right to the output capacitor and routed away from noisy components and traces (e.g., sw line). its trace should be minimized and shielded by a guard-ring connected to the ground. figure 6. pcb layout suggestion v fb guard-ring input capacitor c1 must be placed as close as possible to the ic pins as well as the inductor l1 and output capacitor c2 vias from thermal pad to bottom layer 39mm 47mm cn1=input power supply cn2=enable/disable cn3=input sync. cn4=v out v fb guard-ring input capacitor c1 must be placed as close as possible to the ic pins as well as the inductor l1 and output capacitor c2 vias from thermal pad to bottom layer 39mm 47mm cn1=input power supply cn2=enable/disable cn3=input sync. cn4=v out
ST1S10 layout considerations 15/26 6.1 thermal considerations the leadframe die pad, of ST1S10, is exposed at the bottom of the package and must be soldered directly to a properly designed thermal pad on the pcb, the addition of thermal vias from the thermal pad to an internal gr ound plane will help increase power dissipation. figure 7. pcb layout suggestion common ground node for power ground i in i out power ground common ground node for power ground common ground node for power ground i in i out power ground
diagram ST1S10 16/26 7 diagram figure 8. block diagram
ST1S10 typical performance characteristics 17/26 8 typical performance characteristics unless otherwise specified, refer to the ty pical application circuit under the following conditions: t j = 25c, v in = v in-sw = v in-a = v inh = 12 v, v sync = gnd, v out = 5 v, i out = 10 ma, c in = 4.7 f + 0.1 f, c out = 22 f, l1 = 3.3 h figure 9. voltage feedback vs. temperature figure 10. oscillator frequency vs. temperature figure 11. max duty cycle vs. temperature f igure 12. inhibit thres hold vs. temperature figure 13. reference line regulation vs. temperature figure 14. reference load regulation vs. temperature 760 770 780 790 800 810 820 830 -50 -25 0 25 50 75 100 125 temperature [c] v fb [mv] v in =v inh =12v, v out =0.8v, i out =10ma 760 770 780 790 800 810 820 830 -50 -25 0 25 50 75 100 125 temperature [c] v fb [mv] 760 770 780 790 800 810 820 830 -50 -25 0 25 50 75 100 125 temperature [c] v fb [mv] v in =v inh =12v, v out =0.8v, i out =10ma 0.6 0.7 0.8 0.9 1 1.1 1.2 -50 -25 0 25 50 75 100 125 temperature [c] frequency [mhz] v in-a =v in-sw =v inh =12v, v fb =0v 0.6 0.7 0.8 0.9 1 1.1 1.2 -50 -25 0 25 50 75 100 125 temperature [c] frequency [mhz] v in-a =v in-sw =v inh =12v, v fb =0v 80 82 84 86 88 90 92 -50 -25 0 25 50 75 100 125 temperature [c] duty cycle [%] v in-a =v in-sw =v inh =12v, v fb =0v 80 82 84 86 88 90 92 -50 -25 0 25 50 75 100 125 temperature [c] duty cycle [%] v in-a =v in-sw =v inh =12v, v fb =0v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 -50 -25 0 25 50 75 100 125 temperature [c] v inh (v) v in-a =v in-sw =2.5v, v out =0.8v, i out =10ma 0 0.2 0.4 0.6 0.8 1 1.2 1.4 -50 -25 0 25 50 75 100 125 temperature [c] v inh (v) v in-a =v in-sw =2.5v, v out =0.8v, i out =10ma -0.2 -0.1 0 0.1 0.2 -50 -25 0 25 50 75 100 125 temperature [c] line [%(v out /v in )] v in-a = v in-sw =v inh from 2.5 to 20v, v out =0.8v, i out =10ma -0.2 -0.1 0 0.1 0.2 -50 -25 0 25 50 75 100 125 temperature [c] line [%(v out /v in )] v in-a = v in-sw =v inh from 2.5 to 20v, v out =0.8v, i out =10ma -0.5 -0.2 0.1 0.4 0.7 1 1.3 -25 0 25 50 75 100 125 temperature [c] load [%v out /i out ] v in-a =v in-sw =v inh =12v, i out from 10ma to 3a -0.5 -0.2 0.1 0.4 0.7 1 1.3 -25 0 25 50 75 100 125 temperature [c] load [%v out /i out ] v in-a =v in-sw =v inh =12v, i out from 10ma to 3a
typical performance characteristics ST1S10 18/26 figure 15. on mode quiescent current vs. temperature figure 16. shutdown mode quiescent current vs. temperature figure 17. pmos on resistance vs. temperature figure 18. nmos on resistance vs. temperature figure 19. efficiency vs. temperature figure 20. efficiency vs. output current 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 -50 -25 0 25 50 75 100 125 temperature [c] i q (ma) v in-a =v in-sw =12v, v inh =1.2v, v out =0.8v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 -50 -25 0 25 50 75 100 125 temperature [c] i q (ma) v in-a =v in-sw =12v, v inh =1.2v, v out =0.8v 0 1 2 3 4 5 6 7 -50 -25 0 25 50 75 100 125 temperature [c] i q ( a) v in-a =v in-sw =12v, v inh =gnd, v out =0.8v 0 1 2 3 4 5 6 7 -50 -25 0 25 50 75 100 125 temperature [c] i q ( a) v in-a =v in-sw =12v, v inh =gnd, v out =0.8v 20 70 120 170 220 270 320 -50 -25 0 25 50 75 100 125 temperature [c] r dson -p[m ] v in =12v, i sw =750ma 20 70 120 170 220 270 320 -50 -25 0 25 50 75 100 125 temperature [c] r dson -p[m ] v in =12v, i sw =750ma 50 60 70 80 90 100 110 120 -50 -25 0 25 50 75 100 125 temperature [c] r dson -n[m ] v in =12v, i sw =750ma 50 60 70 80 90 100 110 120 -50 -25 0 25 50 75 100 125 temperature [c] r dson -n[m ] v in =12v, i sw =750ma 50 60 70 80 90 100 -50 -25 0 25 50 75 100 125 temperature [c] efficiency [%] v in-a =v in-sw =v inh =12v, v out =5v, i out =3a 50 60 70 80 90 100 -50 -25 0 25 50 75 100 125 temperature [c] efficiency [%] v in-a =v in-sw =v inh =12v, v out =5v, i out =3a 50 60 70 80 90 100 0 0.5 1 1.5 2 2.5 3 output current [a] efficiency [%] v in-a =v in-sw =v inh =12v, v out =5v, t j =25c 50 60 70 80 90 100 0 0.5 1 1.5 2 2.5 3 output current [a] efficiency [%] v in-a =v in-sw =v inh =12v, v out =5v, t j =25c
ST1S10 typical performance characteristics 19/26 figure 21. efficiency vs. output current figure 22. efficiency vs. output current 50 60 70 80 90 100 0 0.5 1 1.5 2 2.5 3 output current [a] efficiency [%] v in-a =v in-sw =v inh =5v, v out =3.3v, t j =25c 50 60 70 80 90 100 0 0.5 1 1.5 2 2.5 3 output current [a] efficiency [%] v in-a =v in-sw =v inh =5v, v out =3.3v, t j =25c 50 60 70 80 90 100 0 0.5 1 1.5 2 2.5 3 output current [a] efficiency [%] v in-a =v in-sw =v inh =16v, v out =12v, t j =25c 50 60 70 80 90 100 0 0.5 1 1.5 2 2.5 3 output current [a] efficiency [%] v in-a =v in-sw =v inh =16v, v out =12v, t j =25c
package mechanical data ST1S10 20/26 9 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com.
ST1S10 package mechanical data 21/26 dim. mm. inch. min. typ. max. min. typ. max. a 1.70 0.067 a1 0.00 0.15 0.00 0.006 a2 1.25 0.04 9 0.142 b 0. 3 1 0.51 0.012 0.020 c 0.17 0.25 0.007 0.010 d4. 8 04. 9 0 5.00 0.1 89 01 93 0.1 9 7 d1 2.24 3 .10 3 .20 0.0 88 0.122 0.126 e5. 8 0 6.00 6.20 0.22 8 0.2 3 6 0.244 e1 3 . 8 0 3 . 9 0 4.00 0.150 0.154 0.157 e2 1.55 2.41 2.51 0.061 0.0 9 5 0.0 99 e 1.27 0.050 h 0.25 0.50 0.010 0.020 l 0.40 1.27 0.016 0.050 k0 8 0 8 ccc 0.10 0.004 power s o- 8 mechanical data 71 9 5016c
package mechanical data ST1S10 22/26 dim. mm. inch. min. typ. max. min. typ. max. a0. 8 00. 9 0 1.00 0.0 3 1 0.0 3 5 0.0 39 a1 0 0.02 0.05 0 0.001 0.002 a 3 0.20 0.00 8 b 0.2 3 0. 3 00. 38 0.00 9 0.012 0.015 d 3 . 9 0 4.00 4.10 0.154 0.157 0.161 d2 2. 8 2 3 .00 3 .2 3 0.111 0.11 8 0.127 e 3 . 9 0 4.00 4.10 0.154 0.157 0.161 e2 2.05 2.20 2. 3 0 0.0 8 1 0.0 8 7 0.0 9 1 e0. 8 00.0 3 1 l 0.40 0.50 0.60 0.016 0.020 0.024 dfn 8 (4x4) mechanical data 7 8 6 9 65 3 b
ST1S10 package mechanical data 23/26 dim. mm. inch. min. typ. max. min. typ. max. a 33 0 12. 99 2 c 12. 8 1 3 .2 0.504 0.51 9 d 20.2 0.7 9 5 n60 2. 3 62 t 22.4 0. 88 2 ao 8 .1 8 .5 0. 3 1 9 0. 33 5 bo 5.5 5. 9 0.216 0.2 3 2 ko 2.1 2. 3 0.0 8 2 0.0 9 0 po 3 . 9 4.1 0.15 3 0.161 p7. 98 .1 0. 3 11 0. 3 1 9 tape & reel s o- 8 mechanical data
package mechanical data ST1S10 24/26 dim. mm. inch. min. typ. max. min. typ. max. a 33 0 12. 99 2 c 12. 8 1 3 .2 0.504 0.51 9 d 20.2 0.7 9 5 n 99 101 3 . 898 3 . 9 76 t 14.4 0.567 ao 4. 3 5 0.171 bo 4. 3 5 0.171 ko 1.1 0.04 3 po 4 0.157 p 8 0. 3 15 tape & reel qfnxx/dfnxx (4x4) mechanical data
ST1S10 revision history 25/26 10 revision history table 6. document revision history date revision changes 28-aug-2007 1 initial release. 24-sep-2007 2 add r thjc on table 4. 25-oct-2007 3 added new paragraph 6: layout considerations .
ST1S10 26/26 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2007 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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